SH7203 Datasheet, PDF (960/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Controller Area Network (RCAN-TL1)
19.3.3 RCAN-TL1 Control Registers
The following sections describe RCAN-TL1 control registers. The address is mapped as follow.
Important: These registers can only be accessed in Word size (16-bit).
Table 19.2 RCAN-TL1 control registers
Description
Master Control Register
General Status Register
Bit Configuration Register 1
Bit Configuration Register 0
Interrupt Register
Interrupt Mask Register
Error Counter Register
Address
000
002
004
006
008
00A
00C
Name
MCR
GSR
BCR1
BCR0
IRR
IMR
TEC/REC
Access Size (bits)
Word
Word
Word
Word
Word
Word
Word
(1) Master Control Register (MCR)
The Master Control Register (MCR) is a 16-bit read/write register that controls RCAN-TL1.
• MCR (Address = H'000)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
MCR15 MCR14 -
-
-
TST[2:0]
MCR7 MCR6 MCR5 -
Initial value: 1
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R
R
R R/W R/W R/W R/W R/W R/W R
3
2
1
0
- MCR2 MCR1 MCR0
0
0
0
1
R R/W R/W R/W
Bit 15 — ID Reorder (MCR15): This bit changes the order of STDID, RTR, IDE and EXTID of
both message control and LAFM.
Bit15: MCR15
0
1
Description
RCAN-TL1 is the same as HCAN2
RCAN-TL1 is not the same as HCAN2 (Initial value)
Rev. 2.00 Apr. 16, 2008 Page 930 of 1652
REJ09B0313-0200