SH7203 Datasheet, PDF (1169/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
11
SOFRM
0
R/W Frame Number Update Interrupt Output Mode
• When the function controller function is selected:
0: An interrupt is asserted on SOF reception and
timer interpolation.
1: An interrupt is asserted if SOF is damaged or
missing.
• When the host controller function is selected:
0: An interrupt is asserted on SOF transmission.
1: Setting prohibited
Frame number update interrupts are not issued for
μSOF packet detection other than UFRNM = 000 in
UFRMNUM.
10 to 0 FRNM[10:0] H'000 R
Frame Number
The frame number can be confirmed.
When the function controller function is selected, this
module updates the frame numbers at the timing at
which SOF packets are received. If the module
cannot detect an SOF packet because the packet
has been corrupted or for other reasons, the FRNM
value is retained until a new SOF packet is received.
The FRNM bit based on the SOF interpolation timer
is not updated.
Notes: 1. Only 0 can be written to.
2. If OVRN and CRCE sources have occurred, an access cycle of at least 140 ns and 3
bus clock cycles is required in order to clear the bits in succession, not simultaneously.
Table 23.8 Error Information When NRDY Interrupt is Generated in Isochronous OUT
Transfer
Bit Status
OVRN = 1
CRCE = 1
Generating
Timing
Generating Conditions Detected Error
A data packet is
received
A new data packet is
received before reading
of buffer memory is
completed.
Receive data
buffer overrun
A data packet is A CRC error or a bit
Receive packet
received
stuffing error is detected. error
Operation
Receive data is
discarded
Receive data is
discarded
Rev. 2.00 Apr. 16, 2008 Page 1139 of 1652
REJ09B0313-0200