SH7203 Datasheet, PDF (208/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Interrupt Controller (INTC)
2 Icyc + 3 Bcyc + 1 Pcyc
IRQ
9 Icyc
3 Icyc + m1 + m2
RESBANK instruction
FDEEEEEEEEE
m1 m2 m3
Instruction (instruction replacing
interrupt exception handling)
D E EMMME
First instruction in interrupt
exception service routine
FD
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Interrupt acceptance
Figure 6.7 Example of Pipeline Operation when Interrupt is Accepted during RESBANK
Instruction Execution (Register Banking without Register Bank Overflow)
Interrupt acceptance
3 Icyc + m1 + m2
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc
m1 m2 m3
IRQ
Instruction (instruction replacing
interrupt exception handling)
F D E E M M M ^... M
First instruction in interrupt exception
service routine
F ^{... ...} D
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Figure 6.8 Example of Pipeline Operation when IRQ Interrupt is Accepted
(Register Banking with Register Bank Overflow)
Rev. 2.00 Apr. 16, 2008 Page 178 of 1652
REJ09B0313-0200