SH7203 Datasheet, PDF (1388/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 I/O Ports
26.2 Port A
Port A is an input/output port with eight pins as shown in figure 26.1.
Port A
PA7 (input) / AN7 (input) / DA1 (output)
PA6 (input) / AN6 (input) / DA0 (output)
PA5 (input) / AN5 (input)
PA4 (input) / AN4 (input)
PA3 (input) / AN3 (input)
PA2 (input) / AN2 (input)
PA1 (input) / AN1 (input)
PA0 (input) / AN0 (input)
Figure 26.1 Port A
26.2.1 Register Descriptions
Table 26.1 lists the port A registers.
Table 26.1 Register Configuration
Register Name
Abbreviation R/W Initial Value Address
Access Size
Port A data register L PADRL
R
H'00xx
H'FFFE3802 8, 16
26.2.2 Port A Data Register L (PADRL)
PADRL is a 16-bit read-only register that stores port A data. The PA7DR to PA0DR bits
correspond to the PA7/AN7/DA1 to PA0/AN0 pins, respectively. The general input function of
the PA7 to PA0 pins is enabled only when the A/D and D/A converters are halted.
Writing to these bits is ignored, and therefore does not affect the pin state. If these bits are read,
the pin state, not the bit value, is directly returned. Note that, however, this register should not be
read during operation of the A/D or D/A converter. Table 26.2 summarizes PADRL read/write
operation.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
DR DR DR DR DR DR DR DR
Initial value: 0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Note: * Depends on the state of the external pin.
Rev. 2.00 Apr. 16, 2008 Page 1358 of 1652
REJ09B0313-0200