SH7203 Datasheet, PDF (938/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Controller Area Network (RCAN-TL1)
CAN Interface
REC
CRxn
CTxn
Can Core
TEC
BCR
Transmit Buffer
Receive Buffer
Control
Signals
Status
Signals
Micro Processor
Interface
MCR
IRR
GSR
IMR
16-bit peripheral bus
TXPR
TXCR
RXPR
MBIMR
TXACK
ABACK
RFPR
UMSR
Mailbox Control
TTCR0 CMAX_TEW
RFTROFF
TSR
CCR
TCNTR
CYCTR
RFMK
TCMR0
TCMR1
TCMR2
TTTSEL
16-bit Timer
Mailbox0 Mailbox8 Mailbox16 Mailbox24
Mailbox1 Mailbox9 Mailbox17 Mailbox25
Mailbox2 Mailbox10 Mailbox18 Mailbox26
Mailbox3 Mailbox11 Mailbox19 Mailbox27
Mailbox4 Mailbox12 Mailbox20 Mailbox28
Mailbox5 Mailbox13 Mailbox21 Mailbox29
Mailbox6 Mailbox14 Mailbox22 Mailbox30
Mailbox7 Mailbox15 Mailbox23 Mailbox31
Mailbox 0 to 31 (RAM)
control0
LAFM
DATA
Mailbox0 Mailbox8 Mailbox16 Mailbox24
Mailbox1 Mailbox9 Mailbox17 Mailbox25
Mailbox2 Mailbox10 Mailbox18 Mailbox26
Mailbox3 Mailbox11 Mailbox19 Mailbox27
Mailbox4 Mailbox12 Mailbox20 Mailbox28
Mailbox5 Mailbox13 Mailbox21 Mailbox29
Mailbox6 Mailbox14 Mailbox22 Mailbox30
Mailbox7 Mailbox15 Mailbox23 Mailbox31
Mailbox 0 to 31 (register)
control1
Timestamp
Tx-Trigger Time
TT control
[Legend]
n = 0, 1
Note: The core of the RCAN-TL1 is designed with a 32-bit bus system as the basis, but the RCAN-TL1 overall uses a 16-bit bus
interface for communication with the CPU, including the MPI. Longword (32-bit) accesses are converted into two consecutive
word accesses by the bus interface.
Figure 19.1 RCAN-TL1 architecture
Rev. 2.00 Apr. 16, 2008 Page 908 of 1652
REJ09B0313-0200