SH7203 Datasheet, PDF (1570/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 31 Electrical Characteristics
Th
T1
Twx
T2
Tf
CKIO
t_AD1
t_AD1
A25 to A0
t_CSD1
t_CSD1
CSn
WEn
t_RWD1
t_WED1
t_WED1
t_RWD1
RD/WR
tRSD
t_RSD
Read
RD
D31 to D0
t_RDS1
t_RDH1
tRWD1
t_RWD1
Write
RD/WR
t_WDD1
t_WDH1
D31 to D0
BS
DACKn
TENDn*
t_BSD
t_DACD
t_BSD
t_WTH
t_WTH
t_DACD
WAIT
t_WTS
tWTS
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.19 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle,
One Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control))
Rev. 2.00 Apr. 16, 2008 Page 1540 of 1652
REJ09B0313-0200