SH7203 Datasheet, PDF (1137/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Table 23.5 Endian Operation (32-Bit Width Access)
FEND
0
1
Bits 31 to 24
N+0 address
N+3 address
Bits 23 to 16
N+1 address
N+2 address
Bits 15 to 8
N+2 address
N+1 address
Bits 7 to 0
N+3 address
N+0 address
Table 23.6 Endian Operation (16-Bit Width Access)
FEND
Bits 31 to 24
Bits 23 to 16
Bits 15 to 8
Bits 7 to 0
0
Even address
Odd address
Write: Disabled Write: Disabled
Read: Prohibited* Read: Prohibited*
1
Write: Disabled Write: Disabled Odd address
Even address
Read: Prohibited* Read: Prohibited*
Note: * Reading a disabled register in word units is prohibited.
Table 23.7 Endian Operation (8-Bit Width Access)
FEND
Bits 31 to 24
Bits 23 to 16
Bits 15 to 8
Bits 7 to 0
0
Write: Enabled Write: Disabled Write: Disabled Write: Disabled
Read: Enabled Read: Disabled* Read: Disabled* Read: Disabled*
1
Write: Disabled Write: Disabled Write: Disabled Write: Enabled
Read: Prohibited* Read: Prohibited* Read: Prohibited* Read: Enabled
Note: * Reading a disabled register in byte units is prohibited.
Rev. 2.00 Apr. 16, 2008 Page 1107 of 1652
REJ09B0313-0200