SH7203 Datasheet, PDF (23/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

21.3.2 D/A Control Register (DACR) ........................................................................... 1040
21.4 Operation ......................................................................................................................... 1042
21.5 Usage Notes ..................................................................................................................... 1043
21.5.1 Module Standby Mode Setting ........................................................................... 1043
21.5.2 D/A Output Hold Function in Software Standby Mode...................................... 1043
21.5.3 Setting Analog Input Voltage ............................................................................. 1043
21.5.4 D/A Conversion in Deep Standby Mode ............................................................ 1043
Section 22 AND/NAND Flash Memory Controller (FLCTL) ........................1045
22.1 Features............................................................................................................................ 1045
22.2 Input/Output Pins ............................................................................................................. 1049
22.3 Register Descriptions ....................................................................................................... 1050
22.3.1 Common Control Register (FLCMNCR)............................................................ 1051
22.3.2 Command Control Register (FLCMDCR).......................................................... 1054
22.3.3 Command Code Register (FLCMCDR).............................................................. 1057
22.3.4 Address Register (FLADR) ................................................................................ 1058
22.3.5 Address Register 2 (FLADR2) ........................................................................... 1060
22.3.6 Data Counter Register (FLDTCNTR)................................................................. 1061
22.3.7 Data Register (FLDATAR)................................................................................. 1062
22.3.8 Interrupt DMA Control Register (FLINTDMACR) ........................................... 1063
22.3.9 Ready Busy Timeout Setting Register (FLBSYTMR) ....................................... 1069
22.3.10 Ready Busy Timeout Counter (FLBSYCNT)..................................................... 1070
22.3.11 Data FIFO Register (FLDTFIFO)....................................................................... 1071
22.3.12 Control Code FIFO Register (FLECFIFO) ......................................................... 1072
22.3.13 Transfer Control Register (FLTRCR)................................................................. 1073
22.4 Operation ......................................................................................................................... 1074
22.4.1 Access Sequence................................................................................................. 1074
22.4.2 Operating Modes................................................................................................. 1075
22.4.3 Register Setting Procedure.................................................................................. 1076
22.4.4 Command Access Mode ..................................................................................... 1077
22.4.5 Sector Access Mode............................................................................................ 1082
22.4.6 ECC Error Correction ......................................................................................... 1084
22.4.7 Status Read ......................................................................................................... 1085
22.5 Interrupt Sources.............................................................................................................. 1087
22.6 DMA Transfer Specifications .......................................................................................... 1088
Section 23 USB 2.0 Host/Function Module (USB) .........................................1089
23.1 Features............................................................................................................................ 1089
23.2 Input/Output Pins ............................................................................................................. 1091
23.3 Register Description......................................................................................................... 1093
Rev. 2.00 Apr. 16, 2008 Page xxiii of xxx
REJ09B0313-0200