SH7203 Datasheet, PDF (1047/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 A/D Converter (ADC)
Bit
13
12
11 to 8
Bit Name
ADST
⎯
TRGS[3:0]
Initial
Value
0
0
0000
R/W Description
R/W A/D Start
Starts or stops A/D conversion. This bit remains set to 1
during A/D conversion.
0: A/D conversion is stopped
1: Single mode: A/D conversion starts. This bit is
automatically cleared to 0 when A/D conversion ends
on the selected channel.
Multi mode: A/D conversion starts. This bit is
automatically cleared to 0 when A/D conversion is
completed cycling through the selected channels.
Scan mode: A/D conversion starts. A/D conversion is
continuously performed until this bit is cleared to 0 by
software, by a power-on reset as well as by a
transition to deep standby mode, software standby
mode or module standby mode.
R Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Timer Trigger Select
These bits enable or disable starting of A/D conversion
by a trigger signal.
0000: Start of A/D conversion by external trigger input is
disabled
0001: A/D conversion is started by conversion trigger
TRGAN from MTU2
0010: A/D conversion is started by conversion trigger
TRG0N from MTU2
0011: A/D conversion is started by conversion trigger
TRG4AN from MTU2
0100: A/D conversion is started by conversion trigger
TRG4BN from MTU2
1001: A/D conversion is started by ADTRG
Other than above: Setting prohibited
Rev. 2.00 Apr. 16, 2008 Page 1017 of 1652
REJ09B0313-0200