SH7203 Datasheet, PDF (1657/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Main Revisions for this Edition
Item
19.3.3 RCAN-TL1
Control Registers
Page
942
20.5 Interrupt Sources 1031
and DMAC Transfer
Request
23.2 Input/Output Pins 1091
23.3 Register
Description
Table 23.2 Register
Configuration
23.3.4 Test Mode
Register (TESTMODE)
1093
1103
Revision (See Manual for Details)
Description amended
Example 1: For a bit rate of 500 kbps when the fclk frequency
is 32 MHz, satisfy the following conditions: BRP = 3, TSEG1 =
11, TSEG2 = 4. Write H'A300 to BCR1 and H'0001 to BCR0.
Example 2: For a bit rate of 500 kbps when the fclk frequency
is 20 MHz, satisfy the following conditions: BRP = 1, TSEG1 =
6, TSEG2 = 3. Write H'5200 to BCR1 and H'0001 to BCR0.
Description amended
… To make the DMAC transfer all conversion data, set the
ADDR where A/D conversion data is stored as the transfer
source address, set the number of converted channels as the
transfer count, and set the TC bit in the DMA channel control
register (CHCR) to 1.
Description amended
Table 23.1 shows the pin configuration and pin functions of the
USB.
When this module is not in use, handle the pins as follows.
• Be sure to apply power to the power-supply pins
• Connect DP, DM, and VBUS to USBDPV
SS
• Connect REFRIN to USBAPV_CC through a 5.6 kΩ ±1%
resistor
Table amended
Register Name
Test mode register
Abbreviation R/W
TESTMODE R/W
Initial Value Address
Access
Size
H'0100
H'FFFC 1C06 16
Description and bit table amended
TESTMODE is a register that controls the USB test signal
output and the module’s internal USB transceiver during high-
speed operation. This register is initialized by a power-on reset.
A software reset initializes the UTST bits.
Bit: 8
-
Initial value: 1
R/W: R
Rev. 2.00 Apr. 16, 2008 Page 1627 of 1652
REJ09B0313-0200