SH7203 Datasheet, PDF (1652/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Main Revisions for this Edition
Item
16.4.5 SSU Mode
(3) Data Reception
Page
809
Revision (See Manual for Details)
Description amended
… At this time, if the RIE bit in SSER is set to 1, an SSRXI
interrupt is generated. The RDRF bit is automatically cleared to
0 by reading SSRDR.
During continuous slave reception in SSU mode, read the SS
receive data register (SSRDR) before the next reception
operation starts (before the externally connected master device
starts the next transmission). When the next reception
operation starts after the receive data full (RDRF) bit in the SS
status register (SSSR) is set to 1 and before SSRDR is read,
and SSRDR is read before reception of one frame completes,
the conflict/incomplete error (CE) bit in SSSR is set to 1 after
the reception operation ends. In addition, when the next
reception operation starts after RDRF is set to 1 and before
SSRDR is read, and SSRDR is not read before reception of
one frame completes, the receive data is discarded, even
though neither the CE bit nor the overrun error (ORER) bit in
SSSR is set to 1.
Rev. 2.00 Apr. 16, 2008 Page 1622 of 1652
REJ09B0313-0200