SH7203 Datasheet, PDF (1158/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
9
NRDY
8
BRDY
7
VBSTS
6 to 4 DVSQ[2:0]
3
VALID
Initial
Value
0
0
*³
*⁴
0
R/W Description
R
Buffer Not Ready Interrupt Status
This bit is cleared when all of the bits in NRDYSTS
are cleared.
0: NRDY interrupts not generated
1: NRDY interrupts generated
R
Buffer Ready Interrupt Status
This bit is cleared when all of the bits in BRDYSTS
are cleared.
0: BRDY interrupts not generated
1: BRDY interrupts generated
R
VBUS Input Status
This bit monitors the state of the VBUS pin. The
VBUS status needs a control program to prevent
chattering.
0: The VBUS pin is low level
1: The VBUS pin is high level
R
Device State
000: Powered state
001: Default state
010: Address state
011: Configured state
1xx: Suspended state
R/W*¹ Setup Packet Reception
0: Not detected
1: Setup packet reception
Rev. 2.00 Apr. 16, 2008 Page 1128 of 1652
REJ09B0313-0200