SH7203 Datasheet, PDF (223/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 User Break Controller (UBC)
7.3.1 Break Address Register (BAR)
BAR is a 32-bit readable/writable register. BAR specifies the address used as a break condition in
each channel. The control bits CD[1:0] and CP[1:0] in the break bus cycle register (BBR) select
one of the four address buses for a break condition.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
15
BA15
0
R/W
14
BA14
0
R/W
13
BA13
0
R/W
12
BA12
0
R/W
11
BA11
0
R/W
10
BA10
0
R/W
9
BA9
0
R/W
8
BA8
0
R/W
7
BA7
0
R/W
6
BA6
0
R/W
5
BA5
0
R/W
4
BA4
0
R/W
3
BA3
0
R/W
2
BA2
0
R/W
1
BA1
0
R/W
0
BA0
0
R/W
Initial
Bit
Bit Name Value R/W Description
31 to 0 BA31 to BA0 All 0
R/W Break Address
Store an address on the CPU address bus (FAB or
MAB) or internal address bus (ICAB or IDAB)
specifying break conditions.
When the C bus and instruction fetch cycle are
selected by BBR, specify an FAB address in bits BA31
to BA0.
When the C bus and data access cycle are selected by
BBR, specify an MAB address in bits BA31 to BA0.
When the internal CPU bus (I bus) is selected by BBR,
specify an ICAB address in bits BA31 to BA0.
When the internal DMA bus (I bus) is selected by BBR,
specify an IDAB address in bits BA31 to BA0.
Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR to 0.
Rev. 2.00 Apr. 16, 2008 Page 193 of 1652
REJ09B0313-0200