SH7203 Datasheet, PDF (449/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Direct Memory Access Controller (DMAC)
CHCR DMARS DMA Transfer
Request
RS[3:0] MID RID Source
Transfer
DMA Transfer Request Signal Source
Transfer Bus
Destination Mode
1000 001011 11 SSI_3
DMA3 (transmission mode)
DMA3 (reception mode)
Any
SSIRDR3
SSITDR3
Any
Cycle
steal
010100 01 SSU_0
transmission
SSTXI0 (transmission empty or Any
transmission end)
SSTDR0 to Cycle
SSTDR3 steal
10 SSU_0
reception
SSTXI0 (reception full)
SSRDR0 to Any
SSRDR3
010101 01 SSU_1
transmission
SSTXI1 (transmission empty or Any
transmission end)
SSTDR0 to
SSTDR3
10 SSU_1
reception
SSTXI1 (reception full)
SSRDR0 to Any
SSRDR3
011000 01 IIC3_0
transmission
TXI0 (transmission data empty) Any
ICDRT0
10 IIC3_0
reception
RXI0 (reception data full)
ICDRR0 Any
011001 01 IIC3_1
transmission
TXI1 (transmission data empty) Any
ICDRT1
10 IIC3_1
reception
RXI1 (reception data full)
ICDRR1 Any
011010 01 IIC3_2
transmission
TXI2 (transmission data empty) Any
ICDRT2
10 IIC3_2
reception
RXI2 (reception data full)
ICDRR2 Any
011011 01 IIC3_3
transmission
TXI3 (transmission data empty) Any
ICDRT3
Cycle
steal
10 IIC3_3
reception
RXI3 (reception data full)
ICDRR3 Any
100000 01 SCIF_0
TXI0 (transmission FIFO data Any
transmission empty)
SCFTDR_0 Cycle
steal
10 SCIF_0
reception
RXI0 (reception FIFO data full) SCFRDR_0 Any
100001 01 SCIF_1
transmission
TXI1 (transmit FIFO data empty) Any
SCFTDR_1
10 SCIF_1
reception
RXI1 (reception FIFO data full) SCFRDR_1 Any
Rev. 2.00 Apr. 16, 2008 Page 419 of 1652
REJ09B0313-0200