SH7203 Datasheet, PDF (464/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(Rising)
DACK
(Active-high)
CPU
CPU
DMAC
Burst acceptance
Non sensitive period
DMAC
Figure 10.15 Example of DREQ Input Detection in Burst Mode Edge Detection
CKIO
Bus cycle
DREQ
(Overrun 0 at
high level)
DACK
(Active-high)
CPU
CPU
DMAC
1st acceptance
Non sensitive period
2nd
acceptance
Acceptance
start
CKIO
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non sensitive period
DMAC
2nd acceptance
DMAC
3rd
acceptance
Acceptance
start
Acceptance
start
Figure 10.16 Example of DREQ Input Detection in Burst Mode Level Detection
Rev. 2.00 Apr. 16, 2008 Page 434 of 1652
REJ09B0313-0200