SH7203 Datasheet, PDF (1289/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 LCD Controller (LCDC)
24.3.21 LCDC User Specified Interrupt Line Number Register (LDUINTLNR)
LDUINTLNR sets the point where the user specified interrupt is generated. Setting is done in
horizontal line units.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
UINTLN UINTLN UINTLN UINTLN UINTLN UINTLN UINTLN UINTLN UINTLN UINTLN UINTLN
10
9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 11 ⎯
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
10
UINTLN10 0
R/W User Specified Interrupt Generation Line Number
9
UINTLN9 0
R/W Specifies the line in which the user specified interrupt is
8
UINTLN8 0
R/W ^{generated (line units).}
7
UINTLN7 0
R/W
Set (the number of lines in which interrupts are
generated) −1
6
UINTLN6 1
R/W _{Example: Generate the user specified interrupt in the}
5
UINTLN5 0
R/W
80th line.
4
UINTLN4 0
R/W
UINTLN = 160/2 − 1 = 79 = H'04F
3
UINTLN3 1
R/W
2
UINTLN2 1
R/W
1
UINTLN1 1
R/W
0
UINTLN0 1
R/W
Notes: 1. When using the LCD module with STN/TFT display, the setting value of this register
should be equal to lower than the vertical display line number (VDLN) in LDVDLNR.
2. When using the LCD module with DSTN display, the setting value of this register should
be equal to or lower than half the vertical display line number (VDLN) in LDVDLNR. The
user specified interrupt is generated at the point when the LCDC read the specified
piece of image data in lower display from VRAM.
Rev. 2.00 Apr. 16, 2008 Page 1259 of 1652
REJ09B0313-0200