SH7203 Datasheet, PDF (1569/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 31 Electrical Characteristics
CKIO
A25 to A0
CS6
RD/WR
FRAME
Read D31 to D0
Write D31 to D0
BS
DACKn*
TENDn*
WAIT
RD
Tm1
t_AD1
t_CSD1
t_RWD1
Tmd1w
t_FMD
t_WDD1
t_WDD1
t_BSD
tDACD
t_FMD
t_WDH1
t_WDH1
t_WDD1
t_BSD
t_DACD
tWTH
t_WTS
Tmd1
t_AD1
t_CSD1
t_RWD1
t_FMD
tRDS2
t_RDH2
t_WDH1
t_DACD
t_DACD
WEn
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.18 Burst MPX-I/O Interface Bus Cycle Single Read Write
(One Address Cycle, One Software Wait Cycle)
Rev. 2.00 Apr. 16, 2008 Page 1539 of 1652
REJ09B0313-0200