SH7203 Datasheet, PDF (1134/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
3 to 0 UTST[3:0] 0000 R/W Test Mode
Table 23.4 shows test mode operation of this
module. These bits control the USB test signal output
in high-speed mode.
[When the host controller function is selected]
When the host controller function is selected, these
bits may be set after writing 1 to DCFM and DRPD.
Writing to these bits terminates high-speed
operation.
Use the following procedure to set these bits:
(1) Perform a power-on reset.
(2) Set DCFM and DPRD to 1. (It is not necessary to
set HSE to 1.)
(3) Set USBE to 1.
(4) Set the value of these bits according to the test
details.
Use the following procedure to change the values of
these bits:
(1) (In the state following step (4) above) clear USBE
to 0.
(2) Set USBE to 1.
(3) Set the value of these bits according to the test
details.
Note:
When the Test_SE0_NAK (1011) setting is
selected, the module does not output SOF
packets even when UACT is set to 1. When
the Test_Force_Enable (1101) setting is
selected and UACT is set to 1, the module
outputs SOF packets.
When setting the UTST bits, set the PID bits
for all the pipes to NAK. To return to normal
USB communication after test mode setting,
perform a power-on reset.
[When the function controller function is selected]
When the function controller function is selected,
write to these bits according to SetFeature requests
from the USB host during high-speed operation.
Note: The module will not transition to the suspend
state while the setting of these bits is any
value from 0001 to 0100.
Note: * For details, see section 23.5.2, Procedure for Setting the USB Transceiver.
Rev. 2.00 Apr. 16, 2008 Page 1104 of 1652
REJ09B0313-0200