SH7203 Datasheet, PDF (1267/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 LCD Controller (LCDC)
Bit
9, 8
7 to 0
Bit Name
AU[1:0]
⎯
Initial
Value
00
R/W
R/W
All 0 R
Description
Access Unit Select
Select access unit of VRAM. This bit is enabled when
ROT = 1 (rotate the display). When ROT = 0, 16-burst
memory read operation is carried out whatever the AU
setting is.
00: 4-burst
01: 8-burst
10: 16-burst
11: 32-burst
Notes: 1. Above burst lengths are used for 32-bit bus.
For 16-bit bus, the burst lengths are twice
the lengths of 32-bit bus.
2. When displaying a rotated image, the burst
length is limited depending on the number of
column address bits and bus width of
connected SDRAM. For details, see tables
24.4 and 24.5.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Apr. 16, 2008 Page 1237 of 1652
REJ09B0313-0200