SH7203 Datasheet, PDF (1266/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 LCD Controller (LCDC)
24.3.4 LCDC Scan Mode Register (LDSMR)
LDSMR selects whether or not to enable the hardware rotation function that is used to rotate the
LCD panel, and sets the burst length for the VRAM (synchronous DRAM in area 3) used for
display.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
- ROT -
-
-
AU[1:0]
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R R/W R
R
R R/W R/W R
R
R
R
R
R
R
R
Bit
15, 14
Bit Name
⎯
13
ROT
12 to 10 ⎯
Initial
Value R/W
All 0 R
0
R/W
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Rotation Module Select
Selects whether or not to rotate the display by
hardware. Note that the following restrictions are
applied to rotation.
• An STN or TFT panel must be used. A DSTN panel
is not allowed.
• The maximum horizontal (internal scan direction of
the LCD panel) width of the LCD panel is 320.
• Set a binary exponential that exceeds the display
size in LDLAOR. (For example, 256 must be
selected when a 320 × 240 panel is rotated to be
used as a 240 × 320 panel and the horizontal width
of the image is 240 bytes.)
0: Not rotated
1: Rotated 90 degrees rightwards (left side of image is
displayed on the upper side of the LCD module)
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Apr. 16, 2008 Page 1236 of 1652
REJ09B0313-0200