SH7203 Datasheet, PDF (1434/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
7 to 4 ⎯
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
3
RAME3
1
R/W RAM Enable 3 (corresponding area of on-chip RAM
(high-speed): page 3*)
0: Access to on-chip RAM (high-speed) disabled
1: Access to on-chip RAM (high-speed) enabled
2
RAME2
1
R/W RAM Enable 2 (corresponding area of on-chip RAM
(high-speed): page 2*)
0: Access to on-chip RAM (high-speed) disabled
1: Access to on-chip RAM (high-speed) enabled
1
RAME1
1
R/W RAM Enable 1 (corresponding area of on-chip RAM
(high-speed): page 1*)
0: Access to on-chip RAM (high-speed) disabled
1: Access to on-chip RAM (high-speed) enabled
0
RAME0
1
R/W RAM Enable 0 (corresponding area of on-chip RAM
(high-speed): page 0*)
0: Access to on-chip RAM (high-speed) disabled
1: Access to on-chip RAM (high-speed) enabled
Note: * For addresses in each page, see section 27, On-Chip RAM.
Rev. 2.00 Apr. 16, 2008 Page 1404 of 1652
REJ09B0313-0200