SH7203 Datasheet, PDF (320/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
Table 9.5 32-Bit External Device Access and Data Alignment in Big Endian
D31 to
Operation D24
Byte access Data
at 0
7 to 0
Byte access ⎯
at 1
Byte access ⎯
at 2
Byte access ⎯
at 3
Word access Data
at 0
15 to 8
Word access ⎯
at 2
Longword Data
access at 0 31 to 24
Data Bus
D23 to
D16
D15 to
D8
⎯
⎯
Data
7 to 0
⎯
⎯
⎯
Data
7 to 0
⎯
Data
7 to 0
⎯
Data
23 to 16
⎯
Data
15 to 8
Data
15 to 8
WE3,
D7 to D0 DQMUU
⎯
Assert
⎯
⎯
⎯
⎯
Data
7 to 0
⎯
⎯
Assert
Data
7 to 0
Data
7 to 0
⎯
Assert
Strobe Signals
WE2,
DQMUL
WE1,
DQMLU
⎯
⎯
Assert
⎯
⎯
Assert
⎯
⎯
Assert
⎯
⎯
Assert
Assert
Assert
WE0,
DQMLL
⎯
⎯
⎯
Assert
⎯
Assert
Assert
Rev. 2.00 Apr. 16, 2008 Page 290 of 1652
REJ09B0313-0200