SH7203 Datasheet, PDF (1681/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

TCMR1............................................... 977
TCMR2............................................... 977
TCNT.................................................. 490
TCNTR ............................................... 975
TCNTS................................................ 505
TCR .................................................... 451
TDDR ................................................. 506
TDER.................................................. 512
TEC..................................................... 950
TESTMODE..................................... 1103
TGCR.................................................. 503
TGR .................................................... 490
TICCR ................................................ 485
TIER ................................................... 476
TIOR................................................... 458
TITCNT .............................................. 509
TITCR................................................. 507
TMDR................................................. 455
TOCR1................................................ 496
TOCR2................................................ 499
TOER.................................................. 495
TOLBR ............................................... 502
TRWER .............................................. 494
TSR............................................. 479, 972
TSTR .................................................. 491
TSYR .................................................. 492
TTCR0 ................................................ 966
TTTSEL.............................................. 978
TWCR................................................. 513
TXACK0 ............................................ 958
TXACK1 ............................................ 957
TXCR0................................................ 957
TXCR1................................................ 956
TXPR0 ................................................ 955
TXPR1 ................................................ 954
UFRMNUM...................................... 1140
UMSR0 ............................................... 965
UMSR1 ............................................... 964
USBACSWR .................................... 1161
USBADDR ....................................... 1141
USBINDX......................................... 1143
USBLENG ........................................ 1144
USBREQ........................................... 1142
USBVAL........................................... 1143
WRCSR .............................................. 673
WTCNT .............................................. 670
WTCSR............................................... 671
Registers that should not be set in the
USB communication enabled state ....... 1186
Relationship between access size and
number of bursts ..................................... 324
Relationship between refresh requests
and bus cycles ......................................... 343
Reset sequence ........................................ 982
Reset state ................................................. 85
Reset-synchronized PWM mode............. 544
Restoration from bank............................. 182
Restoration from stack ............................ 183
Restriction on DMAC usage ................... 779
Resume interrupt................................... 1181
RISC-type instruction set .......................... 48
Roles of mailboxes.................................. 915
Round to nearest ....................................... 96
Rounding................................................... 96
Round-robin mode .................................. 421
S
SACK interrupt ..................................... 1181
Saving to bank......................................... 181
Saving to stack ........................................ 183
Scan mode............................................. 1025
SCIF interrupt sources ............................ 777
SCIF timing........................................... 1570
SDRAM interface ................................... 308
Searching cache ...................................... 220
Sector access mode ............................... 1082
Self-refreshing......................................... 341
Sending a break signal ............................ 779
Serial bit clock control ............................ 903
Rev. 2.00 Apr. 16, 2008 Page 1651 of 1652
REJ09B0313-0200