SH7203 Datasheet, PDF (1165/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
1
PIPE1NRDY 0
R/W*¹ NRDY Interrupt Status for PIPE1*²
0: Interrupts not generated
1: Interrupts generated
0
PIPE0NRDY 0
R/W*¹ NRDY Interrupt Status for PIPE0*²
0: Interrupts not generated
1: Interrupts generated
Notes: 1. Only 0 can be written to.
2. If multiple sources have occurred, an access cycle of at least 140 ns and 3 bus clock
cycles is required in order to clear the bits in succession, not simultaneously.
Rev. 2.00 Apr. 16, 2008 Page 1135 of 1652
REJ09B0313-0200