SH7203 Datasheet, PDF (702/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 13 Watchdog Timer (WDT)
Bit
5
4, 3
2 to 0
Initial
Bit Name Value R/W Description
TME
0
R/W Timer Enable
Starts and stops timer operation. Clear this bit to 0
when using the WDT in software standby mode or
when changing the clock frequency.
0: Timer disabled
Count-up stops and WTCNT value is retained
1: Timer enabled
⎯
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
CKS[2:0] 000
R/W Clock Select
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (Pφ). The overflow period that is
shown inside the parenthesis in the table is the value
when the peripheral clock (Pφ) is 33 MHz.
Bits 2 to 0
Clock Ratio Overflow Cycle
000:
1 × Pφ
7.7 μs
001:
1/64 × Pφ
500 μs
010:
1/128 × Pφ
1.0 ms
011:
1/256 × Pφ
2.0 ms
100:
1/512 × Pφ
4.0 ms
101:
1/1024 × Pφ 8.0 ms
110:
1/4096 × Pφ 32 ms
111:
1/16384 × Pφ 128 ms
Note: If bits CKS[2:0] are modified when the WDT is
running, the up-count may not be performed
correctly. Ensure that these bits are modified
only when the WDT is not running.
Rev. 2.00 Apr. 16, 2008 Page 672 of 1652
REJ09B0313-0200