SH7203 Datasheet, PDF (132/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 4 Clock Pulse Generator (CPG)
(6) Standby Control Circuit
The standby control circuit controls the states of the clock pulse generator and other modules
during clock switching, or sleep, software standby or deep standby mode.
In addition, the standby control register is provided to control the power-down mode of other
modules. For details on the standby control register, see section 28, Power-Down Modes.
(7) Frequency Control Register (FRQCR)
The frequency control register (FRQCR) has control bits assigned for the following functions:
clock output/non-output from the CKIO pin during software standby mode, the frequency
multiplication ratio of PLL circuit, and the frequency division ratio of the internal clock and the
peripheral clock (Pφ).
Rev. 2.00 Apr. 16, 2008 Page 102 of 1652
REJ09B0313-0200