SH7203 Datasheet, PDF (1284/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 LCD Controller (LCDC)
24.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR)
LDPSPR controls the power supply circuit that provides power to the LCD module. The timing to
start outputting the timing signals to the LCD_VEPWC and LCD_VCPWC pins is specified.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ONA3 ONA2 ONA1 ONA0 ONB3 ONB2 ONB1 ONB0 OFFE3 OFFE2 OFFE1 OFFE0 OFFF3 OFFF2 OFFF1 OFFF0
Initial value: 1
1
1
1
0
1
1
0
0
0
0
0
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15
ONA3
1
R/W LCDC Power-On Sequence Period
14
ONA2
1
R/W Set the period from LCD_VCPWC assertion to starting
13
ONA1
1
R/W ^{output of the display data (LCD_DATA) and timing}
signals (LCD_FLM, LCD_CL1, LCD_CL2, and
12
ONA0
1
R/W _{LCD_M_DISP) in the power-on sequence of the LCD}
module in frame units.
Specify to the value of (the period)-1.
This period is the (a) period in figures 24.4 to 24.7,
Power-Supply Control Sequence and States of the LCD
Module.
11
ONB3
0
R/W LCDC Power-On Sequence Period
10
ONB2
1
R/W Set the period from starting output of the display data
9
ONB1
1
R/W ^{(LCD_DATA) and timing signals (LCD_FLM, LCD_CL1,}
LCD_CL2, and LCD_M_DISP) to the LCD_VEPWC
8
ONB0
0
R/W _{assertion in the power-on sequence of the LCD module}
in frame units.
Specify to the value of (the period)-1.
This period is the (b) period in figures 24.4 to 24.7,
Power-Supply Control Sequence and States of the LCD
Module.
Rev. 2.00 Apr. 16, 2008 Page 1254 of 1652
REJ09B0313-0200