SH7203 Datasheet, PDF (1416/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 27 On-Chip RAM
• Ports
Each page of the on-chip high-speed RAM has two independent read and write ports and is
connected to the internal DMA bus (ID bus), CPU instruction fetch bus (F bus), and CPU
memory access bus (M bus). (Note that the F bus is connected only to the read ports.)
The F bus and M bus are used for access by the CPU, and the ID bus is used for access by the
DMAC.
The on-chip RAM for data retention has one read/write port and is connected to the peripheral
bus.
• Priority
When the same page of the on-chip high-speed RAM is accessed from different buses
simultaneously, the access is processed according to the priority. The priority is ID bus > M
bus > F bus.
Rev. 2.00 Apr. 16, 2008 Page 1386 of 1652
REJ09B0313-0200