SH7203 Datasheet, PDF (1115/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 22 AND/NAND Flash Memory Controller (FLCTL)
22.4.7 Status Read
The FLCTL can read the status register of an AND-type or NAND-type flash memory. The data in
the status register of an AND-type or NAND-type flash memory is input through the I/O7 to I/O0
pins and stored in the bits STAT[7:0] in FLBSYCNT. The bits STAT[7:0] in FLBSYCNT can be
read by the CPU. If a program error or erase error is detected when the status register value is
stored in the bits STAT[7:0] in FLBSYCNT, the STERB bit in FLINTDMACR is set to 1 and
generates an interrupt to the CPU if the STERINTE bit in FLINTDMACR is enabled.
(1) Status Read of AND-Type Flash Memory
The status register of AND-type flash memory can be read by asserting the output enable signal
OE (OE = 0). If programming is executed in command access mode or sector access mode while
the DOSR bit in FLCMDCR is set to 1, the FLCTL automatically asserts the OE signal and reads
the status register of AND-type flash memory. When the status register of AND-type flash
memory is read, the I/O7 to I/O0 pins indicate the following information as described in table
22.3.
Table 22.3 Status Read of AND-Type Flash Memory
I/O
I/O7
I/O6
I/O5
I/O4
I/O3 to I/O0
Status (definition)
Ready/busy
Reserved
Erase check
Program check
Reserved
Description
0: Busy state
1: Ready state
⎯
0: Pass (erased)
1: Fail (erase failure)
0: Pass (programmed)
1: Fail (program failure)
⎯
Rev. 2.00 Apr. 16, 2008 Page 1085 of 1652
REJ09B0313-0200