SH7203 Datasheet, PDF (1541/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 List of Registers
Module Register
Power-On Manual
Name Abbreviation Reset
Reset
Deep
Software Module
Standby Standby Standby Sleep
Power-
Down
Modes
H-UDI*⁹
DSSSR
DSFR
DSRTR
SDIR
Initialized Retained
Initialized Retained
Initialized*¹⁰ Retained
Retained Retained
Initialized
Retained
Initialized
Initialized
Retained
Retained
Retained
Retained
⎯
⎯
⎯
Retained
Retained
Retained
Retained
Retained
Notes: 1. Retains the previous value after an internal power-on reset by means of the WDT.
2. The BN3 to BN0 bits are initialized.
3. Flag handling continues.
4. Counting up continues.
5. Transfer operations can be continued.
6. Bits RTCEN and START are retained.
7. Bits BC3 to BC0 are initialized.
8. Since pin states are read out on the port A data register (PADRL) and the port registers,
values in these registers are neither retained nor initialized.
9. Initialized by TRST assertion or in the Test-Logic-Reset state of the TAP controller.
10. Initialized by RES assertion and retains the previous value after an internal power-on
reset by means of the H-UDI reset assert command or by means of the WDT.
Rev. 2.00 Apr. 16, 2008 Page 1511 of 1652
REJ09B0313-0200