SH7203 Datasheet, PDF (1087/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 22 AND/NAND Flash Memory Controller (FLCTL)
22.3.3 Command Code Register (FLCMCDR)
FLCMCDR is a 32-bit readable/writable register that specifies a command to be issued in
command access or sector access.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15
Initial value: 0
R/W: R/W
14
0
R/W
13
0
R/W
12 11
CMD2[7:0]
0
0
R/W R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
3
CMD1[7:0]
0
0
R/W R/W
2
0
R/W
1
0
R/W
0
0
R/W
Initial
Bit
Bit Name Value R/W Description
31 to 16 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
15 to 8 CMD2[7:0] All 0
R/W Second Command Data
Specify a command code to be issued in the second
command stage.
7 to 0 CMD1[7:0] All 0
R/W First Command Data
Specify a command code to be issued in the first
command stage.
Rev. 2.00 Apr. 16, 2008 Page 1057 of 1652
REJ09B0313-0200