SH7203 Datasheet, PDF (277/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 7)
CSnWCR specifies various wait cycles for memory access. The bit configuration of this register
varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the CSn
space bus control register (CSnBCR). Specify CSnWCR before accessing the target area. Specify
CSnBCR first, then specify CSnWCR.
(1) Normal Space, SRAM with Byte Selection, MPX-I/O
• CS0WCR
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R
R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
SW[1:0]
WR[3:0]
WM
-
-
-
-
HW[1:0]
Initial value: 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R
R
R
R R/W R/W
Bit
Bit Name
31 to 22 ⎯
21, 20 ⎯*
19, 18 ⎯
17, 16 ⎯*
15 to 13 ⎯
Initial
Value
All 0
All 0
All 0
All 0
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Reserved
Set these bits to 0 when the interface for normal space
is used.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Reserved
Set these bits to 0 when the interface for normal space
is used.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Apr. 16, 2008 Page 247 of 1652
REJ09B0313-0200