SH7203 Datasheet, PDF (1682/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Serial communication interface with
FIFO (SCIF) ........................................... 713
Serial Sound Interface (SSI) ................... 867
Setting analog input voltage ....... 1033, 1043
Setting I/O ports for RCAN-TL1.......... 1008
Setting the display resolution................ 1273
Shift instructions....................................... 75
Sign extension of word data ..................... 48
SIGN interrupt ...................................... 1182
Single address mode ............................... 427
Single mode .......................................... 1020
Single read .............................................. 328
Single write............................................. 331
Slave receive operation........................... 852
Slave transmit operation ......................... 849
Sleep mode ................................... 983, 1416
Slot illegal instructions ........................... 134
SOF interpolation function ................... 1218
Software standby mode ........................ 1417
SRAM interface with byte selection....... 354
SSI timing............................................. 1576
SSU Interrupt sources ............................. 822
SSU mode............................................... 805
SSU timing ........................................... 1571
Stack after interrupt exception handling . 173
Stack status after exception handling
ends......................................................... 138
Standby control circuit............................ 102
Status register (SR) ................................... 42
Supported DMA transfers....................... 424
Synchronous serial communication
unit (SSU) ............................................... 783
System control instructions....................... 77
System matrix ......................................... 929
T
T bit .......................................................... 49
TAP controller ...................................... 1433
TDO output timing ............................... 1434
Test mode settings .................................. 980
Rev. 2.00 Apr. 16, 2008 Page 1652 of 1652
REJ09B0313-0200
Time slave............................................... 994
Time trigger control (TT control) ........... 925
Time triggered transmission ................... 989
Timestamp .............................................. 924
Timing to clear an interrupt source ......... 187
Transfer clock ......................................... 800
Transfer rate............................................ 831
Trap instructions ..................................... 134
TTW[1:0] (time trigger window) ............ 926
Tx-trigger control field ........................... 926
Tx-trigger time (TTT) ............................. 925
Types of exception handling and
priority order ........................................... 117
U
UBC timing........................................... 1566
Unconditional branch instructions
with no delay slot ...................................... 49
USB 2.0 host/function module (USB) .. 1089
USB data bus resistor control................ 1163
USB timing ........................................... 1588
User break controller (UBC)................... 189
User break interrupt ................................ 157
User debugging interface (H-UDI) ....... 1429
Using alarm function............................... 709
Using interval timer mode ...................... 679
Using watchdog timer mode ................... 677
V
VBUS interrupt ..................................... 1181
Vector base register (VBR)....................... 43
W
Wait between access cycles .................... 372
Watchdog timer (WDT).......................... 667
WDT timing.......................................... 1569
Write-back buffer
(only for operand cache) ......................... 223