SH7203 Datasheet, PDF (1036/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Controller Area Network (RCAN-TL1)
19.6 DMAC Interface
The DMAC can be activated by the reception of a message in RCAN-TL1 mailbox 0. When
DMAC transfer ends after DMAC activation has been set, flags of RXPR0 and RFPR0 are cleared
automatically. An interrupt request due to a receive interrupt from the RCAN-TL1 cannot be sent
to the CPU in this case. Figure 19.23 shows a DMAC transfer flowchart.
DMAC initialization
DMAC enable register setting
DMAC register information setting
: Settings by user
: Processing by hardware
Message reception in RCAN-TL1
mailbox 0
DMAC activation
No
End of DMAC transfer?
Yes
RXPR and RFPR flags clearing
Transfer counter = 0
No
or DISEL = 1?
Yes
Interrupt to CPU
END
Figure 19.23 DMAC Transfer Flowchart
Rev. 2.00 Apr. 16, 2008 Page 1006 of 1652
REJ09B0313-0200