SH7203 Datasheet, PDF (1417/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 27 On-Chip RAM
27.2 Usage Notes
27.2.1 Page Conflict
When the same page of the on-chip high-speed RAM is accessed from different buses
simultaneously, a conflict on the page occurs. Although each access is completed correctly, this
kind of conflict degrades the memory access speed. Therefore, it is advisable to provide software
measures to prevent such conflicts as far as possible. For example, no conflict will arise if
different pages are accessed by each bus.
27.2.2 RAME and RAMWE Bits
Before disabling memory operation or write access to the on-chip high-speed RAM through the
RAME or RAMWE bit, be sure to read from any address and then write to the same address in
each page; otherwise, the last written data in each page may not be actually written to the RAM.
// For page 0
MOV.L #H'FFF80000,R0
MOV.L @R0,R1
MOV.L R1,@R0
// For page 1
MOV.L #H'FFF84000,R0
MOV.L @R0,R1
MOV.L R1,@R0
// For page 2
MOV.L #H'FFF88000,R0
MOV.L @R0,R1
MOV.L R1,@R0
// For page 3
MOV.L #H'FFF8C000,R0
MOV.L @R0,R1
MOV.L R1,@R0
Figure 27.1 Examples of Read/Write
Rev. 2.00 Apr. 16, 2008 Page 1387 of 1652
REJ09B0313-0200