SH7203 Datasheet, PDF (1665/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Main Revisions for this Edition
Item
Page
28.2.10 Deep Standby 1408,
Control Register
1409
(DSCTR)
28.2.11 Deep Standby 1410
Control Register 2
(DSCTR2)
Revision (See Manual for Details)
Table amended
Bit
Bit Name
7 to 4 ⎯
3
RRAMKP3
2
RRAMKP2
1
RRAMKP1
0
RRAMKP0
Initial
Value
All 0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
On-Chip RAM Storage Area 3 (corresponding area of
on-chip RAM (for data retention): page 3*)
0: The contents of the corresponding on-chip RAM
(for data retention) area are not retained in deep
standby mode.
1: The contents of the corresponding on-chip RAM
(for data retention) area are retained in deep
standby mode.
On-Chip RAM Storage Area 2 (corresponding area of
on-chip RAM (for data retention): page 2*)
0: The contents of the corresponding on-chip RAM
(for data retention) area are not retained in deep
standby mode.
1: The contents of the corresponding on-chip RAM
(for data retention) area are retained in deep
standby mode.
On-Chip RAM Storage Area 1 (corresponding area of
on-chip RAM (for data retention): page 1*)
0: The contents of the corresponding on-chip RAM
(for data retention) area are not retained in deep
standby mode.
1: The contents of the corresponding on-chip RAM
(for data retention) area are retained in deep
standby mode.
On-Chip RAM Storage Area 0 (corresponding area of
on-chip RAM (for data retention): page 0*)
0: The contents of the corresponding on-chip RAM
(for data retention) area are not retained in deep
standby mode.
1: The contents of the corresponding on-chip RAM
(for data retention) area are retained in deep
standby mode.
Description amended
DSCTR2 is an 8-bit readable/writable register that controls the
state of the external bus control pins and specifies the startup
method when returning from deep standby mode. Only byte
access is valid.
Table amended
Initial
Bit
Bit Name Value R/W Description
6
RAMBOOT 0
R/W Selection of Startup Method After Return from Deep
Standby Mode
If deep standby mode is canceled by the MRES, NMI,
or IRQ bit, the program counter (PC) and the stack
pointer (SP) are read from the following addresses,
respectively, in the power-on reset exception
handling.
0: Addresses H'00000000 and H'00000004
1: Addresses H'FFFF8000 and H'FFFF8004
Rev. 2.00 Apr. 16, 2008 Page 1635 of 1652
REJ09B0313-0200