SH7203 Datasheet, PDF (442/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Direct Memory Access Controller (DMAC)
Transfer requests from the various modules specify MID and RID as shown in table 10.4.
Table 10.4 DMARS Settings
Peripheral Module
USB_0
USB_1
SSI_0
SSI_1
SSI_2
SSI_3
SSU_0
SSU_1
IIC3_0
IIC3_1
IIC3_2
IIC3_3
SCIF_0
SCIF_1
SCIF_2
SCIF_3
A/D converter_0
Setting Value for One
Channel ({MID, RID})
H'03
H'07
H'23
H'27
H'2B
H'2F
H'51
H'52
H'55
H'56
H'61
H'62
H'65
H'66
H'69
H'6A
H'6D
H'6E
H'81
H'82
H'85
H'86
H'89
H'8A
H'8D
H'8E
H'B3
MID
B'000000
B'000001
B'001000
B'001001
B'001010
B'001011
B'010100
B'010101
B'011000
B'011001
B'011010
B'011011
B'100000
B'100001
B'100010
B'100011
B'101100
RID
B'11
B'11
B'11
B'11
B'11
B'11
B'01
B'10
B'01
B'10
B'01
B'10
B'01
B'10
B'01
B'10
B'01
B'10
B'01
B'10
B'01
B'10
B'01
B'10
B'01
B'10
B'11
Function
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Rev. 2.00 Apr. 16, 2008 Page 412 of 1652
REJ09B0313-0200