SH7203 Datasheet, PDF (1292/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 LCD Controller (LCDC)
Figure 24.2 shows the valid display and the retrace period.
Hsync Signal
H Total Time
H AddressableVideo
Vsync Time
Back Porch
Top Border
V Addressable
Video
Bottom Border
Front Porch
Active Video =Top/Left Border + Addressable Video + Bottom/Right Border
Total H Blank = Hsync Time + Back Porch + Front Porch
Total V Blank = Vsync Time + Back Porch + Front Porch
HTCN = H Total Time
HDCN = H Addressable Video
HSYNP = H Addressable Video + Right Border + Front Porch
HSYNW = Hsync Time
VTLN = V Total Time
VDLN = V Addressable Video
VSYNP = V Addressable Video + Bottom Border + Front porch
VSYNW = Vsync Time
Figure 24.2 Valid Display and the Retrace Period
24.4.2 Limits on the Resolution of Rotated Displays, Burst Length, and Connected
Memory (SDRAM)
This LCDC is capable of displaying a landscape-format image on a LCD module by rotating a
portrait format image for display by 90 degrees. Only the numbers of colors for each resolution are
supported as shown in tables 24.4 and 24.5. The size of the SDRAM (the number of column
address bits) and its burst length are limited to read the SDRAM continuously.
The number of colors for display, SDRAM column addresses, and LCDC burst length are shown
tables 24.4 and 24.5.
A monochromatic LCD module is necessary for the display of images in the above
monochromatic formats. A color LCD module is necessary for the display of images in the above
color formats.
Rev. 2.00 Apr. 16, 2008 Page 1262 of 1652
REJ09B0313-0200