SH7203 Datasheet, PDF (141/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 4 Clock Pulse Generator (CPG)
Bit
11, 10
9, 8
7 to 5
4
3
2 to 0
Bit Name
⎯
STC[1:0]
⎯
IFC
⎯
PFC[2:0]
Initial
Value
All 0
00
All 0
0
0
011
R/W
R
R/W
R
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Frequency Multiplication Ratio of PLL Circuit
00: × 8 time
01: × 12 times
10: × 16 times
11: Reserved (setting prohibited)
Reserved
These bits are always read as 0. The write value
should always be 0.
Internal Clock Frequency Division Ratio
This bit specifies the frequency division ratio of the
internal clock with respect to the output frequency of
PLL circuit.
0: × 1 time
1: × 1/2 time
Reserved
This bit is always read as 0. The write value should
always be 0.
Peripheral Clock Frequency Division Ratio
These bits specify the frequency division ratio of the
peripheral clock with respect to the output frequency
of PLL circuit.
000: Reserved (setting prohibited)
001: Reserved (setting prohibited)
010: Reserved (setting prohibited)
011: × 1/4 time
100: × 1/6 time
101: × 1/8 time
110: × 1/12 time
Rev. 2.00 Apr. 16, 2008 Page 111 of 1652
REJ09B0313-0200