SH7203 Datasheet, PDF (166/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Exception Handling
5.6.6 FPU Exceptions
FPU exception handling takes place when the V, Z, O, U, or I bit in the FPU enable field (Enable)
of the floating point status/control register (FPSCR) is set to 1. This indicates the occurrence of an
invalid operation exception defined by the IEEE 754 standard, a division-by-zero exception, an
overflow (in the case of an instruction for which this is possible), an underflow (in the case of an
instruction for which this is possible), or an inexact exception (in the case of an instruction for
which this is possible).
The instructions that may trigger FPU exception handling are FADD, FSUB, FMUL, FDIV,
FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC, FCNVDS, FCNVSD, and FSQRT.
FPU exception handling occurs only when the corresponding FPU exception enable bit (Enable) is
set to 1. When an exception source triggered by a floating-point operation is detected, FPU
operation is halted and the occurrence of FPU exception handling is reported to the CPU. When
exception handling starts, the CPU operates as follows:
1. The start address of the exception service routine which corresponds to the FPU exception
handling that occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved on the stack.
3. The program counter (PC) is saved on the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
4. After jumping to the address fetched from the exception handling vector table, program
execution starts. This jump is not a delayed branch.
The FPU exception flag field (Flag) of FPSCR is always updated regardless of whether or not
FPU exception handling has been accepted, and remains set until explicitly cleared by the user
through an instruction. The FPU exception source field (Cause) of FPSCR changes each time a
floating-point instruction is executed.
When the V bit in the FPU exception enable field (Enable) of FPSCR and the QIS bit in FPSCR
are both set to 1, FPU exception handling occurs when qNAN or ±∞ is input to a floating-point
operation instruction source.
Rev. 2.00 Apr. 16, 2008 Page 136 of 1652
REJ09B0313-0200