SH7203 Datasheet, PDF (903/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value
24
DIEN
0
23, 22 CHNL[1:0] 00
21 to 19 DWL[2:0] 000
18 to 16 SWL[2:0} 000
R/W
R/W
R/W
R/W
R/W
Description
Data Interrupt Enable
0: Data interrupt is disabled.
1: Data interrupt is enabled.
Channels
These bits show the number of channels in each
system word.
00: Having one channel per system word
01: Having two channels per system word
10 Having three channels per system word
11: Having four channels per system word
Data Word Length
Indicates the number of bits in a data word.
000: 8 bits
001: 16 bits
010: 18 bits
011: 20 bits
100: 22 bits
101: 24 bits
110: 32 bits
111: Reserved
System Word Length
Indicates the number of bits in a system word.
000: 8 bits
001: 16 bits
010: 24 bits
011: 32 bits
100: 48 bits
101: 64 bits
110: 128 bits
111: 256 bits
Rev. 2.00 Apr. 16, 2008 Page 873 of 1652
REJ09B0313-0200