SH7203 Datasheet, PDF (1461/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 29 User Debugging Interface (H-UDI)
29.3 Register Descriptions
The H-UDI has the following registers.
Table 29.2 Register Configuration
Register Name
Bypass register
Instruction register
Abbreviation R/W
SDBPR
⎯
SDIR
R
Initial Value
⎯
H'EFFD
Address
⎯
H'FFFE2000
Access
Size
⎯
16
29.3.1 Bypass Register (SDBPR)
SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to BYPASS
mode, SDBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined.
29.3.2 Instruction Register (SDIR)
SDIR is a 16-bit read-only register. It is initialized by TRST assertion or in the TAP test-logic-
reset state, and can be written to by the H-UDI irrespective of the CPU mode. Operation is not
guaranteed if a reserved command is set in this register. The initial value is H'EFFD.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TI[7:0]
-
-
-
-
-
-
-
-
Initial value: 1* 1* 1* 0* 1* 1* 1* 1* 1
1
1
1
1
1
0
1
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Note: * The initial value of the TI[7:0] bits is a reserved value. When setting a command, the TI[7:0] bits must be set to another value.
Bit
Bit Name
15 to 8 TI[7:0]
7 to 2 ⎯
Initial
Value
R/W
11101111* R
All 1
R
Description
Test Instruction
The H-UDI instruction is transferred to SDIR by a
serial input from TDI.
For commands, see table 29.3.
Reserved
These bits are always read as 1.
Rev. 2.00 Apr. 16, 2008 Page 1431 of 1652
REJ09B0313-0200