SH7203 Datasheet, PDF (1271/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 LCD Controller (LCDC)
24.3.8 LCDC Palette Control Register (LDPALCR)
LDPALCR selects whether the CPU or LCDC accesses the palette memory. When the palette
memory is being used for display operation, display mode should be selected. When the palette
memory is being written to, color-palette setting mode should be selected.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
- PALS -
-
- PALEN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit
Bit Name
15 to 5 ⎯
4
PALS
3 to 1 ⎯
0
PALEN
Initial
Value R/W
All 0 R
0
R
All 0 R
0
R/W
Description
Reserved
These bits always read as 0. The write value should
always be 0.
Palette State
Indicates the access right state of the palette.
0: Display mode: LCDC uses the palette
1: Color-palette setting mode: The host (CPU) uses the
palette
Reserved
These bits are always read as 0. The write value should
always be 0.
Palette Read/Write Enable
Requests the access right to the palette.
0: Request for transition to normal display mode
1: Request for transition to color palette setting mode
Rev. 2.00 Apr. 16, 2008 Page 1241 of 1652
REJ09B0313-0200