D12320VF25V Datasheet, PDF (997/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TIOR3H—Timer I/O Control Register 3H
Appendix B Internal I/O Registers
H'FE82
TPU3
Bit
:
Initial value :
Read/Write :
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
TGR3A I/O Control
0 0 0 0 TGR3A Output disabled
1
is output
compare
Initial output is
1 0 ^{register 0 output}
0 output at compare match
1 output at compare match
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is
1 output
0 output at compare match
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR3A Capture input
is input source is
1 _{capture TIOCA3 pin}
1 × ^register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1××
Capture input
Input capture at TCNT4 count-up/
source is channel
4/count clock
count-down
× : Don't care
TGR3B I/O Control
0 0 0 0 TGR3B Output disabled
is output
1
1
0
compare
register
Initial output is
0 output
0 output at compare match
1 output at compare match
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR3B Capture input
is input source is
1 _{capture TIOCB3 pin}
1 × ^register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1××
Capture input
source is channel
4/count clock
Input capture at TCNT4 count-up/
count-down^*
× : Don't care
Note: * When bits TPSC2 to TPSC0 in TCR4 are set to B'000, and φ/1 is used as
the TCNT4 count clock, this setting is invalid and input capture does not
occur.
Rev.7.00 Feb. 14, 2007 page 963 of 1108
REJ09B0089-0700