D12320VF25V Datasheet, PDF (291/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 I/O Ports
8.6.3 Pin Functions
Modes 4 and 5: In modes 4 and 5, the lower 4 bits of port A are designated as address outputs
automatically.
Port A pin functions in modes 4 and 5 are shown in figure 8.6.
Port A
A19 (output)
A18 (output)
A17 (output)
A16 (output)
Figure 8.6 Port A Pin Functions (Modes 4 and 5)
Mode 6^*: In mode 6*, port A pins function as address outputs or input ports. Input or output can
be specified on an individual bit basis. Setting PADDR bits to 1 makes the corresponding port A
pins address outputs, while clearing the bits to 0 makes the pins input ports.
Port A pin functions in mode 6 are shown in figure 8.7.
Port A
When PADDR = 1
A19 (output)
A18 (output)
A17 (output)
A16 (output)
When PADDR = 0
PA3(input)
PA2(input)
PA1(input)
PA0(input)
Figure 8.7 Port A Pin Functions (Mode 6)
Mode 7^*: In mode 7*, port A pins function as I/O ports. Input or output can be specified for each
pin on an individual bit basis. Setting PADDR bits to 1 makes the corresponding port A pins
output ports, while clearing the bits to 0 makes the pins input ports.
Port A pin functions in mode 7 are shown in figure 8.8.
Rev.7.00 Feb. 14, 2007 page 257 of 1108
REJ09B0089-0700