D12320VF25V Datasheet, PDF (1056/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
SMR1—Serial Mode Register 1
H'FF80
Smart Card Interface 1
Bit
:
7
6
5
4
3
2
1
0
GM
BLK
PE
O/E BCP1 BCP0 CKS1 CKS0
Initial value :
0
0
0
0
0
0
0
0
Read/Write : R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select
0 0 φ clock
1 φ/4 clock
1 0 φ/16 clock
1 φ/64 clock
Base Clock Pulse
BCP1 BCP0 Base Clock Pulse
0 0 32 clocks
1 64 clocks
1 0 372 clocks
1 256 clocks
Parity Mode
(Set to 1 when using the smart card interface)
0 Even parity^*1
1 Odd parity^*2
Notes: 1. When even parity is selected, the parity bit added to
transmit data makes an even number of 1s in the
transmitted character and parity bit combined. Receive
data must have an even number of 1s in the received
character and parity bit combined.
2. When odd parity is selected, the parity bit added to
transmit data makes an odd number of 1s in the
transmitted character and parity bit combined. Receive
data must have an odd number of 1s in the received
character and parity bit combined.
Parity Enable
0 Setting prohibited
1 Parity bit addition and checking enabled*
Note: * When the PE bit is set to 1, the parity (even or odd) specified by
the O/E bit is added to transmit data before transmission. In
reception, the parity bit is checked for the parity (even or odd)
specified by the O/E bit.
Block Transfer Mode Select
0 Normal smart card interface mode
GSM Mode
1 Block transfer mode
0 Normal smart card interface mode operation
· TEND flag generated 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit
· Clock output on/off control only
1 GSM mode smart card interface mode operation
· TEND flag generated 11.0 etu after beginning of start bit
· Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control
Note: etu (Elementary Time Unit): Time for transfer of 1 bit
Rev.7.00 Feb. 14, 2007 page 1022 of 1108
REJ09B0089-0700