D12320VF25V Datasheet, PDF (335/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 16-Bit Timer Pulse Unit (TPU)
Section 9 16-Bit Timer Pulse Unit (TPU)
9.1 Overview
The chip has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels.
9.1.1 Features
• Maximum 16-pulse input/output
⎯ A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,
and two each for channels 1, 2, 4, and 5), each of which can be set independently as an
output compare/input capture register
⎯ TGRC and TGRD for channels 0 and 3 can also be used as buffer registers
• Selection of 8 counter input clocks for each channel
• The following operations can be set for each channel:
⎯ Waveform output at compare match: Selection of 0, 1, or toggle output
⎯ Input capture function: Selection of rising edge, falling edge, or both edge detection
⎯ Counter clear operation: Counter clearing possible by compare match or input capture
⎯ Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously
⎯ Simultaneous clearing by compare match and input capture possible
⎯ Register simultaneous input/output possible by counter synchronous operation
⎯ PWM mode: Any PWM output duty can be set
⎯ Maximum of 15-phase PWM output possible by combination with synchronous operation
• Buffer operation settable for channels 0 and 3
⎯ Input capture register double-buffering possible
⎯ Automatic rewriting of output compare register possible
• Phase counting mode settable independently for each of channels 1, 2, 4, and 5
⎯ Two-phase encoder pulse up/down-count possible
• Cascaded operation
⎯ Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel
4) overflow/underflow
• Fast access via internal 16-bit bus
⎯ Fast access is possible via a 16-bit bus interface
Rev.7.00 Feb. 14, 2007 page 301 of 1108
REJ09B0089-0700