D12320VF25V Datasheet, PDF (91/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
(6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit
(#xx:16), or 32-bit (#xx:32) immediate data as an operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
(7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and
added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch
address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the
displacement is added is the address of the first byte of the next instruction, so the possible
branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to
+16384 words) from the branch instruction. The resulting value should be an even number.
(8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
instruction code contains an 8-bit absolute address specifying a memory operand. This memory
operand contains a branch address. The upper bits of the absolute address are all assumed to be 0,
so the address range is 0 to 255 (H'000000 to H'0000FF).
In advanced mode the memory operand is a longword operand, the first byte of which is assumed
to be all 0 (H'00).
Note that the first part of the address range is also the exception vector area. For further details,
refer to section 4, Exception Handling.
Specified
by @aa:8
Reserved
Branch address
Advanced Mode
Figure 2.10 Branch Address Specification in Memory Indirect Mode
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