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Section 2 CPU
2.6.2 Instructions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU
can use.
Table 2.2 Combinations of Instructions and Addressing Modes
Addressing Modes
Function Instruction
Data
transfer
MOV
BWL BWL BWL BWL BWL BWL B BWL ⎯ BWL ⎯ ⎯ ⎯ ⎯
POP, PUSH ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ WL
LDM, STM
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
L
MOVFPE,
⎯⎯
⎯
⎯⎯
⎯
⎯
B
⎯
⎯⎯
⎯
⎯
⎯
MOVTPE^*1
Arithmetic ADD, CMP BWL BWL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
operations _SUB
WL BWL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
ADDX, SUBX B
B
⎯
⎯⎯
⎯
⎯
⎯⎯
⎯
⎯⎯
⎯
⎯
ADDS, SUBS ⎯
L
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
INC, DEC
⎯ BWL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
DAA, DAS
⎯ B ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
MULXU,
DIVXU
⎯ BW ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
MULXS,
DIVXS
⎯ BW ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
NEG
⎯ BWL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
EXTU, EXTS ⎯ WL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
TAS^*2
⎯⎯ B ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Logic
AND, OR,
operations XOR
BWL BWL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
NOT
⎯ BWL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Shift
⎯ BWL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Bit manipulation
⎯B
B ⎯⎯⎯ B
B ⎯ B ⎯⎯⎯⎯
Branch
Bcc, BSR
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
⎯⎯
JMP, JSR
⎯⎯⎯⎯⎯⎯⎯⎯
⎯⎯⎯
⎯
RTS
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
System
control
TRAPA
RTE
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
SLEEP
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
LDC
B
B WWWW⎯W⎯W⎯⎯⎯⎯
STC
⎯
B
W
W
W
W⎯W⎯W
⎯⎯⎯⎯
ANDC,
B
⎯
⎯
⎯⎯
⎯
⎯
⎯⎯
⎯
⎯⎯
⎯⎯
ORC, XORC
NOP
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Block data transfer
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ BW
Legend:
Size refers to the operand size.
B: Byte
W: Word
L: Longword
Notes: 1. Cannot be used in the H8S/2319 Group.
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev.7.00 Feb. 14, 2007 page 43 of 1108
REJ09B0089-0700