D12320VF25V Datasheet, PDF (148/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Interrupt Controller
As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range
from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding
interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority
level, level 7, by setting H'7.
When interrupt requests are generated, the highest-priority interrupt according to the priority
levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt
mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if
the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to
the CPU.
5.2.3 IRQ Enable Register (IER)
Bit
:
Initial value :
R/W
:
7
IRQ7E
0
R/W
6
IRQ6E
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
0
IRQ0E
0
R/W
IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests
IRQ7 to IRQ0.
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to
IRQ0 are enabled or disabled.
Bit n
IRQnE
0
1
Description
IRQn interrupts disabled
IRQn interrupts enabled
(Initial value)
(n = 7 to 0)
Rev.7.00 Feb. 14, 2007 page 114 of 1108
REJ09B0089-0700